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CY62167DV20 MoBL2TM
16-Mb (1024K x 16) Static RAM
Features
* Very high speed: 55 ns and 70 ns * Wide voltage range: 1.65V to 2.2V * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 18 mA @ f = fMAX * Ultra-low standby power * Easy memory expansion with CE1, CE2, and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Packages offered in a 48-ball FBGA toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then das pins (A0 through A 19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the ad Reading from the device is accomplished by taking Chip Enable 1 (CE 1) LOW and Chip Enable 2 (CE 2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description [1]
The CY62167DV20 is a high-performance CMOS static RAM organized as 1024K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DATA IN DRIVERS
ROW DECODER
1024K x 16 RAM ARRAY 2048 x 512 x 16
SENSE AMPS
I/O 0-I/O7 I/O 8-I/O15
COLUMN DECODER
A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19
BHE WE OE BLE
CE2 CE1
Power-down Circuit
BHE BLE
CE2 CE1
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress SemiconductorCorporation Document #: 38-05327 Rev. *B
*
3901 North First Street
*
SanJose, CA 95134 * 408-943-2600 Revised January 2, 2004
CY62167DV20 MoBL2TM
Pin Configuration[2, 3.]
1 BLE I/O 8 I/O 9 VS S VCC I/O14 I/O 15 A18
2 OE BHE I/O10 I/O 11
3 A0 A3 A5 A17
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE 1 I/O1 I/O 3 I/O4 I/O5 WE A11
6 CE 2 I/O 0 I/O2 Vcc Vss I/O 6 I/O7 NC A B C D E F G H
I/O12 DNU I/O 13 A19 A8 A14 A 12 A9
Notes: 2. DNU pins are to be connected to V SS or left open. 3. NC pins are not connected on the die.
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ......................................... -0.2V to V CCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State [4, 5.] ......................... -0.2V to V CCMAX + 0.2V DC Input Voltage [4, 5.] ......................-0.2V to V CCMAX + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.....................................................> 200 mA
Operating Range
Range Industrial Ambient Temperature (TA) -40 oC to +85oC VCC[6] 1.65V to 2.2V
Product Portfolio
Power Dissipation Operating, Icc (mA) VCC Range(V) Product CY62167DV20L CY62167DV20LL Min. 1.65 1.65 Typ. 1.8 1.8 Max. 2.2 2.2 Speed (ns) 55 70 55 70 1.5 5 f = 1 MHz Typ. [7] 1.5 Max. 5 f = fMAX Typ.[7] Max. 18 15 18 15 35 30 35 30 Standby, ISB2 (A) Typ.[7] 2.5 2.5 2.5 2.5 Max. 40 40 30 30
DC Electrical Characteristics (over the operating range)
CY62167DV20-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled Vcc = 2.2V, IOUT = 0mA, CMOS level Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 -0.2 -1 -1 18 1.5 2.5 2.5 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 35 5 40 30 1.4 -0.2 -1 -1 15 1.5 2.5 2.5 Typ.[7] Max. CY62167DV20-70 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 30 5 40 30 A Typ.[7] Max. Unit V V V V A A mA
VCC Operating Supply f = fMAX = 1/t RC Current f = 1 MHz
ISB1
Automatic CE CE1 > VCC - 0.2V, CE2 < L Power-down Current - 0.2V, V IN > VCC - 0.2V, V IN LL CMOS Inputs < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) Automatic CE CE1 > VCC - 0.2V, CE2 < L Power-down Current - 0.2V, VIN > VCC - 0.2V or LL CMOS Inputs VIN < 0.2V, f = 0, V CC=2.2V
ISB2
2.5 2.5
40 30
2.5 2.5
40 30
A
Capacitance [8]
Parameter CIN COUT
4. 5. 6. 7. 8.
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ)
Max. 8 10
Unit pF pF
V IL(min.) = -2.0V for pulse durations less than 20 ns. V IH(max) = VCC + 0.75V for pulse durations less than 20 ns. Full device AC operation assumes a 100 s ramp time from 0 to V cc (min) and 100 s wait time after Vcc stabilization. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = V CC(typ.), T A = 25C. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[8] Thermal Resistance (Junction to Case)[8] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT GND CL = 30 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT
Parameters R1 R2 R TH V TH
ALL INPUT PULSES VCC Typ 10% R2 Rise Time: 1 V/ns Fall Time: 1 V/ns 90% 90% 10%
TH EVENIN EQUIVALENT
RTH
V
UNIT V
1.8 V 1350 0 1080 0 6000 0.80
Data Retention Characteristics
Parameter VDR ICCDR tCDR [8] tR[9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC=1.0V, CE1 > VCC - 0.2V, CE2 < L 0.2V, V IN > VCC - 0.2V or VIN < 0.2V LL 0 tRC Conditions Min. 1.0 Typ. Max. 2.2 15 10 ns ns Unit V A
Data Retention Waveform [10]
DATA RETENTION MODE VCC CE1 or BHE .BLE or CE2 VCC(min.) tCDR VDR > 1.0V VCC(min.) tR
Notes: 9. Full device operation requires linear VCC ramp from V DR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 10. BHE . BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Switching Characteristics (over the operating range)[11]
CY62167DV20-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[10] tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle [14] Write Cycle Time CE 1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[12, 13] 10 WE HIGH to Low Z[12] 55 40 40 0 0 40 45 25 0 20 10 70 60 60 0 0 45 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE 1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[12] OE HIGH to High Z
[12, 13]
CY62167DV20-70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 55
Max.
55 10 55 25 5 20 10 20 0 55 55 10 20 Z[12, 13]
CE 1 LOW or CE2 HIGH to Low Z[12] CE 1 HIGH or CE2 LOW to High CE 1 LOW or CE2 HIGH to Power-up CE 1 HIGH or CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[12] BLE/BHE HIGH to High-Z[12, 13]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Notes: 11. Test conditions assume signal transition time of 2 ns or less, timing reference levels of V CC(typ.)/2 , input pulse levels of 0 to V CC(typ.), and output loading of the specified I O L. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, t HZBE is less than t LZBE, tHZOE is less than tLZOE, and tHZWE is less than t LZWE for any given device. 13. tHZOE, t HZCE, t HZBE , and tHZWE transitions are measured when the outputs enter a high-impedance state. 14. The internal Write time of the memory is defined by the overlap of WE, CE 1 = V IL, BHE and/or BLE = V IL . 15. Device is continuously selected. OE, CE1 = V IL, CE2 = V IH 16. WE is HIGH for Read cycle.
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS t RC
CE 1
t PD t HZCE t ACE
CE2
BHE / BLE
t DBE t LZBE
OE
t HZBE
t DOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE t LZCE tPU 50% DATA VALID
t HZOE HIGH IMPEDANCE ICC 50% ISB
Write Cycle No. 1 (WE Controlled)[14, 18, 19, 20]
t WC ADDRESS t SCE CE1 CE2 t AW t SA WE t PWE t HA
BHE/BLE
t BW
OE t SD DATA I/O
DON'T CARE
t HD
DATA VALID IN t HZOE
Notes: 17. Address valid prior to or coincident with CE 1, BHE, BLE transition LOW and CE 2 transition HIGH. 18. Data I/O is high-impedance if OE = V IH . 19. If CE 1 goes HIGH or CE 2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 20. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Switching Waveforms (continued)
Write Cycle No. 2 ( CE1 or CE2 Controlled)[14, 18, 19, 20]
t WC ADDRESS t SCE CE1
CE2
t SA
t AW t PWE
t HA
WE
BHE/BLE
t BW
OE tS D DATA I/O
DON'T CARE
t HD
DATA IN VALID t HZOE
Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20]
tWC ADDRESS tSCE CE1
CE2 tA W tSA WE tS D DATA I/O
DON'T CARE
tHA tPWE
tHD
DATA VALID IN tHZWE tLZWE
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Switching Waveforms (continued) Write Cycle No. 4(BHE/BLE Controlled, OE LOW)[19]
t WC ADDRESS
CE 1 CE 2 t SCE t AW t BW BHE/ BLE t SA WE t PWE t SD DATA I/O
DON'T CARE
t HA
t HD
DATA VALID IN
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Input / Outputs High Z High Z High Z Data Out (I/O0- I/O15) Data Out (I/O0- I/O7); High Z (I/O8- I/O15) High Z (I/O0- I/O7); Data Out (I/O8- I/O15) High Z High Z High Z Data In Data In High Z High Z Data In (I/O0- I/O15) (I/O0- I/O7); (I/O8- I/O15) (I/O0- I/O7); (I/O8- I/O15) Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (I SB ) Standby (I SB ) Standby (I SB ) Active (I CC) Active (I CC) Active (I CC) Active (I CC) Active (I CC) Active (I CC) Active (I CC) Active (I CC) Active (I CC)
Document #: 38-05327 Rev. *B
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CY62167DV20 MoBL2TM
Ordering Information
Speed (ns) 55 70 Ordering Code CY62167DV20L-55BVI CY62167DV20LL-55BVI CY62167DV20L-70BVI CY62167DV20LL-70BVI Package Name BV48B BV48B BV48B BV48B Package Type 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) Industrial Operating Range Industrial
Package Diagrams
48-lead VFBGA (8 x 9.5 x 1 mm) BV48B
51-85178-**
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05327 Rev. *B
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62167DV20 MoBL2TM
Document History Page
Document Title: CY62167DV20 MoBL2TM 16-Mb (1024K x 16) Static RAM Document Number: 38-05327 REV. ** A B ECN NO. 118407 123691 131496 Issue Date 09/30/02 02/11/03 11/25/03 Orig. of Change GUG DPM XRJ/LDZ New Data Sheet Changed Advance Information to Preliminary Added package diagram Changed from Preliminary to Final Added MoBL2TM to title Added package name BV48B Description of Change
Document #: 38-05327 Rev. *B
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